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1 ? fn7421.3 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2005, 2006, 2010. all rights reserved. all other trademarks mentioned are the property of their respective owners. el4340, el4342 500mhz triple, multiplexing amplifiers the el4340, el4342 are fixed unity gain mux amps featuring high slew rates and excellent bandwidth for video switching. these devices feature a high impedance output state (hiz) that enables the outputs of multiple devices to be wired together. a power-down mode (en able ) is included to turn off un-needed circuitry in power sensitive applications. the en able pin, when pulled high, sets the el4340, el4342 into standby power mode - consuming just 18mw. an added feature in the el4340 is a latch enable function (le ) that allows independent logic control using a common logic bus. related literature ? an1182, el4340eval1 evaluation board user's guide ? an1193, isl59445/el4342e1 evaluation board user's guide features ? triple 2:1 and 4:1 multiplexers for rgb ? internally set gain-of-1 ? high speed three-state outputs (hiz) ? power-down mode (en able ) ? latch enable (el4340) ? 5v operation ? 870 v/s slew rate ? 500mhz bandwidth ? typical supply currents 10ma/ch (el4340) and 15.3ma/ch (el4342) ? pb-free (rohs compliant) applications ? hdtv/dtv analog inputs ? video projectors ? computer monitors ? set-top boxes ? security video ? broadcast video equipment ordering information part number (notes 1, 2, 3) part marking package (pb-free) pkg. dwg. # el4340iuz el4340iuz 24 ld qsop mdp0040 el4342ilza 4342ilz 32 ld 5x6 qfn l32.5x6a el4340iuz-eval evaluation board EL4342ILZA-EVAL evaluation board notes: 1. add ?-t13? or ?-t7? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plasti c packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity le vel (msl), please see device information page for el4340 , el4342 . for more information on msl please see techbrief tb363 . table 1. channel select logic table el4340 s0 enable hiz le output 0000ino (a, b, c) 1 0 0 0 in1 (a, b, c) x 1 x x power-down x0 1 x high z x 0 0 1 last s0 state preserved table 2. channel select logic table el4342 s1 s0 enable hiz output 0 0 0 0 in0 (a, b, c) 0 1 0 0 in1 (a, b, c) 1 0 0 0 in2 (a, b, c) 1 1 0 0 in3 (a, b, c) x x 1 x power-down xx 0 1 high z data sheet october 18, 2010
2 fn7421.3 october 18, 2010 pinouts el4340 (24 ld qsop) top view el4342 (32 ld qfn) top view functional diagram el4340 functional diagram el4342 gnd b nic gnd a in0a in0b nic le enable hiz outa nic in0c v+ outb 1 2 3 4 16 15 14 13 5 6 7 12 11 9 8 10 20 19 18 17 24 23 22 21 in1b nic in1a outc v- nic in1c gnd c s0 nic a v =1 a v =1 a v =1 latched on high le nic = no internal connectio n thermal pad 25 24 23 22 21 20 19 32 31 30 29 28 10 11 12 13 14 1 2 3 4 5 6 7 in1a nic in1b nic in1c gnd b in2a enable nic v+ outa v- outb outc gnd a in0a nic in0b nic in2c gnd c in3a nic in3b 8 9 18 17 15 27 16 26 s0 s1 nic in3c nic in2b in0c hiz a v =1 a v =1 a v =1 thermal pad internally connected to v-. nic = no internal connection pad must be tied to v- out decode in0(a, b, c) in1(a, b, c) c c le s0 enable d l q d l q en0 en1 hiz a logic high on le will latch the last s0 state. this logic state is preserved when cycling hiz or enable functions. amplifier bias decode in0(a, b, c) in1(a, b, c) in2(a, b, c) in3(a, b, c) s0 s1 en0 en1 en3 en2 out hiz enable amplifier bias el4340, el4342
3 fn7421.3 october 18, 2010 absolute maxi mum ratings (t a = +25c) thermal information supply voltage (v+ to v-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11v input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . v- -0.5v, v+ +0.5v supply turn-on slew rate . . . . . . . . . . . . . . . . . . . . . . . . . . . 1v/s digital & analog input current (note 6) . . . . . . . . . . . . . . . . . . 50ma output current (continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . 50ma esd rating human body model (per mil-st d-883 method 3 015.7). . . .2500v machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300v thermal resistance (typical) ja (c/w) jc (c/w) 32 ld qfn package (notes 4, 5). . . . . 35 1.3 to 8 24 ld qsop package (note 4) . . . . . . 88 n/a storage temperature range . . . . . . . . . . . . . . . . . .-65c to +150c ambient operating temperature . . . . . . . . . . . . . . . .-40c to +85c operating junction temperature . . . . . . . . . . . . . . .-40c to +125c power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see curves pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adversely im pact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the component mounted on a high effe ctive thermal conductivity test board with ?direct attach? fea tures. see tech brief tb379 . 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 6. if an input signal is applied before the supplies are powered up, the input current must be limited to these maximum values. important note: all parameters having min/max specifications are guaranteed. typical values are for information purposes only. u nless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a electrical specifications v+ = +5v, v- = -5v, gnd = 0v, t a = +25c, input video = 1v p-p and r l = 500 to gnd, c l = 5pf unless otherwise specified. parameter description conditions min typ max unit general +i s enabled enabled supply current (el4340) no load, v in = 0v, enable low 26 30 34 ma enabled supply current (el4342) 39 46 50 ma -i s enabled enabled supply current (el4340) no load, v in = 0v, enable low -32 -30 -24 ma enabled supply current (el4342) -48 -46 -36.5 ma +i s disabled disabled supply current (el4340) no load, v in = 0v, enable high 2.3 2.8 3.3 ma disabled supply current (el4342) no load, v in = 0v, enable high 3 3.5 4 ma -i s disabled disabled suppl y current no load, v in = 0v, enable high 10 100 a v out positive and negative output swing v in = 3.5v, r l = 500 3.1 3.4 v i out output current r l = 10 to gnd 80 135 ma v os output offset voltage (el4340) -15 7 +15 mv v os output offset voltage (el4342) -10 +10 mv ib input bias current v in = 0v -1 -2 -3 a r out hiz output resistance hiz = logic high 1.4 m r out enabled output resistance hiz = logic low 0.2 r in input resistance v in = 3.5v 10 m a cl or a v voltage gain v in = 1.5v, r l = 500 0.98 0.99 1.02 v/v i tri output current in three-state v out = 0v 8 15 22 a logic v ih input high voltage (logic inputs) 2 v v il input low voltage (logic inputs) 0.8 v i ih input high current (logic inputs) v h = 5v 215 270 320 a i il input low current (logic inputs) v l = 0v 2 3 a el4340, el4342
4 fn7421.3 october 18, 2010 ac general t s 0.1% settling time step = 1v 10 ns psrr (el4340) power supply rejection ratio dc, psrr v+ and v- combined 52 72 db psrr (el4342) power supply rejection ratio dc, psrr v+ and v- combined 52 56 db iso channel isolation f = 10mhz, ch-c h x-talk and off-isolation, c l = 1.5pf 75 db dg differential gain error ntc-7, rl = 150, c l = 1.5pf 0.02 % dp differential phase error ntc-7, rl = 150, c l = 1.5pf 0.02 bw -3db bandwidth c l = 1.5pf 500 mhz fbw 0.1db bandwidth c l = 1.5pf 60 mhz 0.1db bandwidth cl = 4.7pf 120 mhz sr slew rate 25% to 75%, r l = 150 , input enabled, c l = 1.5pf 870 v/s switching characteristics v glitch el4340 channel-to-channel switching glitch v in = 0v, c l = 1.5pf 40 mv p-p enable switching glitch v in = 0v c l = 1.5pf 300 mv p-p hiz switching glitch v in = 0v c l = 1.5pf 200 mv p-p v glitch el4342 channel-to-channel switching glitch v in = 0v c l = 1.5pf 20 mv p-p enable switching glitch v in = 0v c l = 1.5pf 200 mv p-p hiz switching glitch v in = 0v c l = 1.5pf 200 mv p-p t sw-l-h channel switching time low to high 1.2v logic threshold to 10% movement of analog output 18 ns t sw-h-l channel switching time high to low 1.2v logic threshold to 10% movement of analog output 20 ns tr, tf rise and fall time 10% to 90% 1.1 ns tpd propagation delay 10% to 10% 0.9 ns t lh latch enable hold time (el4340 only) le = 0 10 ns electrical specifications v+ = +5v, v- = -5v, gnd = 0v, t a = +25c, input video = 1v p-p and r l = 500 to gnd, c l = 5pf unless otherwise specified. (continued) parameter description conditions min typ max unit typical performance curves v s = 5v, r l = 500 to gnd, t a = +25c, unless otherwise specified. figure 1. gain vs frequency vs c l figure 2. gain vs frequency vs r l -10 -8 -6 -4 -2 0 2 4 6 8 10 1 10 100 1k frequency (mhz) normalized gain (db) c l = 2.2pf c l = 6.2pf c l = 7.3pf c l = 4.7 pf c l = 1.5pf c l = 11.5pf c l includes 1.5pf board capacitance c l = 16.5pf source power = -20 dbm -5 -4 -3 -2 -1 0 1 2 3 4 5 1 10 100 1k frequency (mhz) normalized gain (db) r l = 150 r l = 500 r l = 100 r l = 1k source power = -20dbm el4340, el4342
5 fn7421.3 october 18, 2010 figure 3. 0.1db gain vs frequency figure 4. r out vs frequency figure 5. el4340 transient response figure 6. el4342 transient response figure 7. el4340 crosstalk and off-isolation figure 8. el4342 crosstalk and off-isolation typical performance curves v s = 5v, r l = 500 to gnd, t a = +25c, unless otherwise specified. (continued) 10 100 1k frequency (mhz) source power = -20dbm -0.7 -0.6 -0.4 -0.3 -0.1 0.0 0.1 -0.2 -0.5 1 c l = 4.7pf c l = 1.5pf 0.2 -0.8 normalized gain (db) 100 10 1 0.1 0.1 1 10 100 1k frequency (mhz) output resistance ( ) output voltage (v) time (5ns/div) 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 c l = 1.5pf r l = 500 0.8 -0.8 output voltage (v) time (5ns/div) 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 c l = 1.5pf r l = 500 -0.8 0.8 frequency (mhz) -10 -30 -50 (db) 0.1 1 10 100 1k -70 -90 input x to output y crosstalk 0 -20 -40 -60 -80 -100 off isolation input x to output x frequency (mhz) -10 -30 -50 (db) 0.1 1 10 100 1k -70 -90 0 -20 -40 -60 -80 -100 off isolation input x to output x input x to output y crosstalk el4340, el4342
6 fn7421.3 october 18, 2010 figure 9. el4340 psrr channels a, b, c figure 10. el4342 psrr channels a, b, c figure 11. channel to channel switching glitch v in =0v figure 12. channel to channel transient response v in =1v figure 13. enable switching glitch v in = 0v figure 14. enable transient response v in = 1v typical performance curves v s = 5v, r l = 500 to gnd, t a = +25c, unless otherwise specified. (continued) frequency (mhz) 0 -10 -30 psrr (db) 0.3 1 10 100 1k -50 -70 10 -20 -40 -60 -80 20 psrr (v+) psrr (v-) frequency (mhz) 0 -10 -30 psrr (db) 0.3 1 10 100 1k -50 -70 10 -20 -40 -60 20 -80 psrr (v+) psrr (v-) 1v/div 20mv/div v out a, b, c 20ns/div 0 0 v in = 0v s0, s1 50 term. 1v/div 0.5v/div 20ns/div 0 0 v in = 1v v out a, b, c s0, s1 50 term. 1v/div 100mv/div 20ns/div 0 0 v in = 0v v out a, b, c enable 50 term. v in = 1v 1v/div 1v/div 20ns/div 0 0 v out a, b, c enable 50 term. el4340, el4342
7 fn7421.3 october 18, 2010 figure 15. hiz switching glitch v in = 0v figure 16. hiz transient response v in = 1v figure 17. input noise vs frequency (output a, b, c) figure 18. package power dissipation vs ambient temperature figure 19. package power dissipation vs ambient temperature typical performance curves v s = 5v, r l = 500 to gnd, t a = +25c, unless otherwise specified. (continued) 1v/div 200mv/div 10ns/div 0 0 v in = 0v v out a, b, c hiz 50 term. v in = 1v 1v/div 1v/div 10ns/div 0 0 v out a, b, c 50 term. hiz 60 50 40 30 20 10 0 100 1k 10k 100k frequency (hz) voltage noise (nv/ hz ) jedec jesd51-7 high effective thermal conductivity test board-qfn exposed diepad soldered to pcb per jesd51-5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 25 50 75 100 150 ambient temperature (c) power dissipation (w) q ja = 35c/w qfn32 125 85 q ja = 88c/w qsop24 1.136w 2.857w jedec jesd51-3 low effective thermal conductivity test board 1.2 1.0 0.8 0.6 0.4 0.2 0 0 25 50 75 100 150 ambient temperature (c) power dissipation (w) 125 85 ja = 125c/w qfn32 ja = 115c/w qsop24 870mw 758mw el4340, el4342
8 fn7421.3 october 18, 2010 pin descriptions el4342 (32 ld qfn) el4340 (24 ld qsop) pin name equivalent circuit description 1 8 in1a circuit 1 channel 1 input for output amplifier "a" 2, 4, 8, 13, 15, 24, 28, 30 4, 7, 9, 13, 15, 24 nic n ot i nternally c onnected; it is recommended these pins be tied to ground to minimize crosstalk. 3 10 in1b circuit 1 channel 1 input for output amplifier "b" 5 12 in1c circuit 1 channel 1 input for output amplifier "c" 6 5 gndb circuit 4 ground pin for output amplifier ?b? 7 na in2a circuit 1 channel 2 input for output amplifier "a" 9 na in2b circuit 1 channel 2 input for output amplifier "b" 10 na in2c circuit 1 channel 2 input for output amplifier "c" 11 11 gndc circuit 4 ground pin for output amplifier ?c? 12 na in3a circuit 1 channel 3 input for output amplifier "a" 14 na in3b circuit 1 channel 3 input for output amplifier "b" 16 na in3c circuit 1 channel 3 input for output amplifier "c" 17 na s1 circuit 2 channel selection pin msb (binary logic code) 18 14 s0 circuit 2 channel selection pin. lsb (binary logic code) 19 17 outc circuit 3 output of amplifier ?c? 20 18 outb circuit 3 output of amplifier ?b? 21 16 v- circuit 4 negativpine power supply 22 20 outa circuit 3 output of amplifier ?a? 23 19 v+ circuit 4 positive power supply 25 22 enable circuit 2 device enable (active low). internal pu ll-down resistor ensures the device will be active with no connection to this pin. a logic high on this pin puts device into power- down mode. in power-down mode only logic ci rcuitry is active. all logic states are preserved post power-down. this state is not recommended for logic control where more than one mux-amp share the same video output line. -23le circuit 2 device latch enable on the el4340. a logic high on le will latch the last (s0, s1) logic state. hiz and enable functions are not latched with the le pin. 26 21 hiz circuit 2 output disable (active high). inter nal pull-down resistor ensures the device will be active with no connection to this pin. a logic high, puts the outputs in a high impedance state. use this state to control logic when more than one mux-amp share the same video output line. 27 6 in0c circuit 1 channel 0 for output amplifier "c" 29 3 in0b circuit 1 channel 0 for output amplifier "b" 31 1 in0a circuit 1 channel 0 for output amplifier "a" 32 2 gnda circuit 4 ground pin for output amplifier ?a? in v+ v- logic v+ v- gnd 33k 21k + - 1.2v v+ v- out circuit 3 circuit 1 circuit 2 v- v+ gndb capacitively coupled esd clamp gndc gnda circuit 4 v- thermal heat sink pad ~1m substrate el4340, el4342
9 fn7421.3 october 18, 2010 figure 20a illustrates the optimum output load for testing ac performance. figure 20b illustrates the optimun output load when connecting to 50 input terminated equipment. application information general the el4340, el4342 triple 2:1 and 4:1 mux amps are ideal as the matrix element of high performance switchers and routers. key features incl ude buffered high impedance analog inputs and excellent ac performance at output loads down to 150 for video cable-driving. the unity-gain current feedback output amplifiers are stable operating into capacitive loads and bandwidth is optimized with a load of 5pf in parallel with a 500 . total output capacitance can be split between the pcb capacitance and an external load capacitor. ground connections for the best isolation and crosstalk rejection, all gnd pins and nic pins must connect to the gnd plane. control signals s0, s1, enable , le , hiz - these are binary coded, ttl/cmos compatible control inpu ts. the s0, s1 pins select the inputs. all three amplifie rs are switched simultaneously from their respective inputs. the enable , le , hiz pins are used to disable the part to save power, latch in the last logic state and three-state the output amplifiers, respectively. for control signal rise and fall times less than 10ns the use of termination resistors close to the part will minimize transients coupled to the output. power-up considerations the esd protection circuits use internal diodes from all pins the v+ and v- supplies. in addition, a dv/dt- triggered clamp is connected between the v+ and v- pins, as shown in the equivalent circuits 1 through 4 section of the pin description table. the dv/dt triggered clamp imposes a maximum supply turn-on slew rate of 1v/s. damaging currents can flow for power supply rates-of-ri se in excess of 1v/s, such as during hot plugging. under these conditions, additional methods should be employed to ens ure the rate of rise is not exceeded. consideration must be given to the order in which power is applied to the v+ and v- pins, as well as analog and logic input pins. schottky diodes (motorola mbr0550t or equivalent) connected from v+ to ground and v- to ground (figure 21) will shunt damaging currents away from the internal v+ and v- esd diodes in the event that the v+ supply is applied to the device before the v- supply. if positive voltages are applied to the logic or analog video input pins before v+ is applied, current will flow through the internal esd diodes to the v+ pin. the presence of large decoupling capacitors and the loading effect of other circuits connected to v+, can result in damaging currents through the esd diodes and other active circuits within the device. therefore, adequate current lim iting on the digital and analog inputs is needed to prevent damage during the time the voltages on these inputs are more positive than v+. ac test circuits figure 20a. test circuit with optimal output load figure 20b. test circuit for measuring with 50 or 75 input terminated equipment figure 20c. backloaded test circuit for video cable application. bandwidth and linearity for r l less than 500 will be degraded. figure 20. test circuits el4340, el4342 c l 50 v in 500 r l 5 p f or 75 el4340, el4342 r s c l v in 475 test 5 p f 50 or 75 50 or 75 50 or 75 equipment el4340, el4342 r s c l v in 50 or 75 test 5pf 50 or 75 50 or 75 equipment v+ v+ v- v- v+ v- v+ v- logic control gnd in0 in1 s0 out external circuits schottky protection v+ v- power gnd signal logic v+ supply v- supply de-coupling caps figure 21. schottky protection circuit el4340, el4342
10 fn7421.3 october 18, 2010 hiz state an internal pull-down resistor ensures the device will be active with no connection to the hiz pin. the hiz state is established within approximately 15ns (figure 16) by placing a logic high (>2v) on the hiz pin. if the hiz state is selected, the output is a high impedance 1.4m with approximately 1.5pf in parallel with a 10 a bias current from the output. use this state when more than one mux shares a common output. in the hiz state the output is three-stated, and maintains its high z even in the presence of high slew rates. the supply current during this state is same as the active state. enable and power-down states the enable pin is active low. an internal pull-down resistor ensures the device will be active with no connection to the enable pin. the power-down state is established within approximately 80ns (figure 14), if a logic high (>2v) is placed on the enable pin. in the power-down state, the output has no leakage but has a large variable capacitance (on the order of 15pf), and is capable of being back-driven. under this condition, large in coming slew rates can cause fault currents of tens of ma. do not use this state as a high impedance output when several mux amps share the same output line. le state the el4340 is equipped with a latch enable pin. a logic high (>2v) on the le pin latches the last logic state. this logic state is preserved when cycling hiz or enable functions. limiting the output current no output short circuit current li mit exists on these parts. all applications need to limit the output current to less than 50ma. adequate thermal heat si nking of the parts is also required. application example figure 22 illustrates the use of the el4342, two isl84517 spst switches and one nc7st00p5x nand gate to mux 3 different component video signals and one rgb video signal. the spdt switches provide the sync signal for the rgb video and disconnects the sync signal for the component signal. pc board layout the ac performance of this circuit depends greatly on the care taken in designing the pc board. the following are recommendations to achieve optimum high frequency performance from your pc board. ? the use of low inductance components such as chip resistors and chip capacitors is strongly recommended. ? minimize signal trace lengths. trace inductance and capacitance can easily limit circuit performance. avoid sharp corners, use rounded corners when possible. vias in the signal lines add inductance at high frequency and should be avoided. pcb traces greater than 1" begin to exhibit transmission line characteristics with signal rise/fall times of 1ns or less. high frequency performance may be degraded for traces greater than one inch, unless strip line are used. ? match channel-channel analog i/o trace lengths and layout symmetry. this will minimize propagation delay mismatches. ? maximize use of ac de-coupled pcb layers. all signal i/o lines should be routed over continuous ground planes (i.e. no split planes or pcb gaps under these lines). avoid vias in the signal i/o lines. ? use proper value and location of termination resistors. termination resistors should be as close to the device as possible. ? when testing use good quality connectors and cables, matching cable types and keeping cable lengths to a minimum. ? minimum of 2 power supply de-coupling capacitors are recommended (1000pf, 0.01f) as close to the devices as possible - avoid vias between the cap and the device because vias add unwanted inductance. larger caps can be farther away. when vias are required in a layout, they should be routed as far away from the device as possible. ? the nic pins are placed on both sides of the input pins. these pins are not internally connected to the die. it is recommended these pins be tied to ground to minimize crosstalk. the qfn package requires additional pcb layout rules for the thermal pad the thermal pad is electrically connected to v- supply through the high resistance ic substrate. its primary function is to provide heat sinking for the ic. however, because of the connection to the v- supply through the substrate, the thermal pad must be tied to the v- supply to prevent unwanted current flow to the thermal pad. do not tie this pin to gnd as this could result in large back biased currents flowing between gnd and v-. the el4342 uses the package with pad dimensions of d2 = 2.48mm and e2 = 3.4mm. maximum ac performance is achieved if the thermal pad is attached to a dedicated de-couple d layer in a multi-layered pc board. in cases where a dedicated layer is not possible, ac performance may be reduc ed at upper frequencies. the thermal pad requirements are proportional to power dissipation and ambient temperature. a dedicated layer eliminates the need for individual thermal pad area. when a dedicated layer is not possible a 1? x 1? pad area is sufficient for the el4342 that is dissi pating 0.5w in +50c ambient. pad area requirements should be evaluated on a case by case basis. el4340, el4342
11 fn7421.3 october 18, 2010 figure 22. application showing three ypbpr channels and one rgb+hv channel pb1 pb2 pb3 g pr1 pr2 pr3 b inoa in1a in2a in3a inob in1b in2b in3b inoc in1c in2c in3c 31 1 7 12 29 3 9 14 27 5 10 16 el4342il s0 s1 h sync v sync 18 17 outc 19 20 outb outa 22 v- v+ 5v -5v 0.1f 0.1f 1nf 1nf y1 y2 y3 r r1 75 r2 75 r3 75 r5 75 r7 75 r9 75 r4 75 r6 75 r8 75 r11 75 r10 75 r12 75 gnda gndb gndc nic nic nic nic nic nic nic nic 32 6 11 2 4 8 13 15 24 28 30 isl84517ih-t com 1 nc 2 v- v+ 5v -5v 0.1f 0.1f 1nf 1nf in 4 nc7st00p5x out 4 input 1 input 2 5v 0.1f 1nf 5v gnd 23 21 enable logic inputs 25 hiz 26 r16 500 r17 500 r18 500 3 5 3 5 isl84517ih-t com 1 nc 2 v- v+ 5v -5v 0.1f 0.1f 1nf 1nf in 4 3 5 sc70 sot-23 sot-23 qfn optional schottky protection el4340, el4342
12 fn7421.3 october 18, 2010 el4340, el4342 quad flat no-lead plastic package (qfn) micro lead frame pl astic package (mlfp) pin #1 i.d. mark 2 1 3 (n-2) (n-1) n (n/2) 2x 0.075 top view (n/2) ne 2 3 1 pin #1 i.d. (n-2) (n-1) n b l n leads bottom view detail x plane seating n leads c see detail "x" a1 (l) n leads & exposed pad 0.10 side view 0.10 b a m c c b a e 2x 0.075 c d 3 5 7 (e2) (d2) e 0.08 c c (c) a 2 c l32.5x6a (one of 10 packages in mdp0046) 32 lead quad flat no-lead plastic package (compliant to jedec mo-220) symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 0.00 0.02 0.05 - d 5.00 bsc - d2 2.48 ref - e 6.00 bsc - e2 3.40 ref - l 0.45 0.50 0.55 - b 0.17 0.22 0.27 - c 0.20 ref - e 0.50 bsc - n 32 ref 4 nd 7 ref 6 ne 9 ref 5 rev 1 2/09 notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. tiebar view shown is a non-functional feature. 3. bottom-side pin #1 i.d. is a diepad chamfer as shown. 4. n is the total number of terminals on the device. 5. ne is the number of terminals on the ?e? side of the package (or y-direction). 6. nd is the number of terminals on the ?d? side of the package (or x-direction). nd = (n/2)-ne. 7. inward end of terminal may be s quare or circular in shape with radius (b/2) as shown.
13 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn7421.3 october 18, 2010 el4340, el4342 quarter size outline plast ic packages family (qsop) 0.010 c a b seating plane detail x e e1 1 (n/2) (n/2)+1 n pin #1 i.d. mark b 0.004 c c a see detail "x" a2 44 gauge plane 0.010 l a1 d b h c e a 0.007 c a b l1 mdp0040 quarter size outline plastic packages family symbol inches tolerance notes qsop16 qsop24 qsop28 a 0.068 0.068 0.068 max. - a1 0.006 0.006 0.006 0.002 - a2 0.056 0.056 0.056 0.004 - b 0.010 0.010 0.010 0.002 - c 0.008 0.008 0.008 0.001 - d 0.193 0.341 0.390 0.004 1, 3 e 0.236 0.236 0.236 0.008 - e1 0.154 0.154 0.154 0.004 2, 3 e 0.025 0.025 0.025 basic - l 0.025 0.025 0.025 0.009 - l1 0.041 0.041 0.041 basic - n 16 24 28 reference - rev. f 2/07 notes: 1. plastic or metal protrusions of 0.006? maximum per side are not included. 2. plastic interlead protrusions of 0.010? maximum per side are not included. 3. dimensions ?d? and ?e1? are measured at datum plane ?h?. 4. dimensioning and tolerancing per asme y14.5m-1994.

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